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- Formal Verification of Analog AI Hardware (FAI)
- Energy Optimised Analog Circuits for Deep Neural Networks (ENERGICS)
- Formal Abstraction and Verifcation of Analog Circuits (faveAC)
- Analog-Coverage in der Nanoelektronik (ANCONA)
- Hochverlässliches selbst-adaptives Mixed-Signal Multi-Core System-on-Chip(MixedCoreSoC)
- Mikrosystem-Design-Flow für KMUs (MiDes)
- Code-Coverage for Verilog-A Models
- ASDeX (Formalized Specification of Analog Circuits)
- FAC'14 Benchmark Suite
- Equivalence Checking (Vera) Simulation (gnucap-uf)
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- Formal Verification of Analog AI Hardware (FAI)
- Energy Optimised Analog Circuits for Deep Neural Networks (ENERGICS)
- Formal Abstraction and Verifcation of Analog Circuits (faveAC)
- Analog-Coverage in der Nanoelektronik (ANCONA)
- Hochverlässliches selbst-adaptives Mixed-Signal Multi-Core System-on-Chip(MixedCoreSoC)
- Mikrosystem-Design-Flow für KMUs (MiDes)
- Research Activities
- Code-Coverage for Verilog-A Models
- ASDeX (Formalized Specification of Analog Circuits)
- FAC'14 Benchmark Suite
- Equivalence Checking (Vera) Simulation (gnucap-uf)
- Joint Robotics Lab
- Downloads
- Cadence Academic Network
- Studentische Projekte
- Abgeschlossene Projekte
Funktionale Verifikation von Systemen (FEST)
Das Projekt funktionale Verifikation von Systemen (FEST) ist ein Clusterforschungsprojekt des edacentrums. Das Projekt wird an an sechs deutschen Universitäten verteilt bearbeitet.
