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- S. Huss, S. Klupsch A new approach to mixed-signal model refinement by code Refactoring methods Forum on Specification & Design Languages (FDL), Frankfurt, 2003
- J. Romberg, C. Grimm Refinement of Hybrid Systems from Formal Models to Design Languages Languages for System Specification, Kluwer Academic Publisher, C. Grimm (editor), 2004
- A. Vachoux, C. Grimm, K. Einwich Towards Analog and Mixed-Signal SoC Design with SystemC-AMS IEEE International Workshop on Electronic Design, Test and Applications (DELTA), Perth, Australia, 2004
- C. Grimm, W. Heupke, C. Meise, K. Waldschmidt Refinement of Mixed-Signal Systems with Affine Arithmetic Design and Test in Europe (DATE), Paris, 2004
- G. Stehr, H. Graeb, K. Antreich Analog performance space exploration by Fourier-Motzkin Elimination with application to hierarchical Sizing IEEE/ACM International Conference on Computer-Aided Design (ICCAD), USA, 2004
- Kaiping Zeng, Sorin A. Huss RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis University Booth at DATE, Munich, Germany, 2005
- R. Schroll, C. Grimm, K. Waldschmidt Verfeinerung von Mixed-Signal Systemen mit polymorphen Signalen ANALOG, Hannover, 2005
- C. Grimm, W. Heupke, K. Waldschmidt Analysis of Mixed-Signal Systems with Affine Arithmetic IEEE Transactions on Computer Aided Design of Circuits and Systems (TCAD), (1), 2005
- Kaiping Zeng, Sorin A. Huss RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis IEEE Computer Society anual Symposium on VLSI, Tampa, Florida, USA, 2005
- C. Grimm, R. Schroll, K. Waldschmidt Refinement of Mixed-Signal Systems: Between HEAVEN and HELL Advances in Design and Specification Languages for SoCs. Kluwer Academic Publisher, 2005
- D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann Deterministic Approaches to Analog Performance Space Exploration ACM/IEEE Design Automation Conference (DAC), 2005
- K. Zeng, S. A. Huss Towards Analog Circuit Synthesis: Refinement of Behavioural Models by Means of Code Refactoring Methods IEEK Int. SoC Design Conf., Seoul, Korea, 2005
- J. Zou, D. Mueller, H. Graeb, U. Schlichtmann, E. Hennig, R. Sommer Fast Automatic Sizing of a Charge Pump Phase-Locked Loop based on Behavioral Models IEEE Int. Behavioral Modeling and Simulation Conference (BMAS), 2005
- Xiaoying Wang, Lars Hedrich An Approach to Topology Synthesis of Analog Circuits Using Hierarchical Blocks and Symbolic Analysis Proc. of Asia and South Pacific Design Automation Conference (ASPDAC), 2005
- Xiaoying Wang Analog Circuits: Explorative Synthesis of Topologies University Booth at DATE, Munich, Germany, 2006
- Roland Jancke CHAMELEON University Booth at DATE, Munich, Germany, 2006
- Kaiping Zeng, Sorin A. Huss Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques The 7th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, March 27-29, 2006
- S. Huss Analog Circuit Synthesis: A Search for the Holy Grail? IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Griechenland, Mai 2006 21-24, 2006
- D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann Fast evaluation of analog circuit structures by polytopal approximations IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Griechenland, Mai 2006 21-24, 2006
- R. Jancke, P. Schwarz Supporting Analog Synthesis by Abstracting Circuit Behavior Using a Modeling Methodology IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Griechenland, Mai 2006 21-24, 2006
- Xiaoying Wang, Lars Hedrich Hierarchical Exploration and Selection of Transistor-Topologies for Analog Circuit Design IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Griechenland, Mai 2006 21-24, 2006
- Kaiping Zeng, Sorin A. Huss Architecture Refinements by Code Refactoring of Behavioral VHDL-AMS Models IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Griechenland, Mai 2006 21-24, 2006
- Ralf Popp Dem Analog-Entwickler das Leben erleichtern Elektronik, 23 2003
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